The present invention relates to a clock distribution circuit which distributes clock signals to a plurality of storage elements in a synchronous sequential circuit.
A synchronous sequential circuit is a logical circuit including storage elements such as flip-flops and delay elements which operate synchronizing with respective clock signals. An LSI (large-scale integrated circuit) chip on which such a synchronous sequential circuit is mounted must distribute clock signals to all the storage elements at a minimum time difference. The time difference between clock signals is called a clock skew, and a clock distribution circuit with zero clock skew has been sought.
The well-known grid type clock distribution circuit is mainly used in a gate array and provided with a mesh clock wiring interconnection which is installed on the entire chip, and a clock buffer which is disposed in the periphery of the chip or in the center of the mesh clock interconnection so as to drive the clock interconnection. This type of circuit has a drawback of increasing interconnection capacitance. The well-known tree type clock distribution circuit has a tree structure clock interconnection which is composed of a clock buffer as the root, and flip-flops as the ends of the branches. This type of circuit includes subsidiary buffers each disposed at a branch point so as to keep a balance between the delays of clock signals on both sides of the branch point. This type of circuit has a drawback that the design and adjustment are difficult.
In order to overcome these problems, Japanese Laid-open Patent Application No. 4-229634 has suggested a clock distribution circuit which has the following structure. Two clock interconnections adjacent to each other are arranged in parallel on the chip and each interconnection is formed into a loop. One end of one clock interconnection is driven by a clock buffer and the opposite end of the other clock interconnection is driven by another clock buffer. The two clock interconnections are connected to a clock branch circuit at any position so as to mix and buffer the clock signals on both clock interconnections. The clock distribution circuit has succeeded in reducing a clock skew as the result that a flip-flop receives a clock signal which is generated by mixing the clock signals having a delay difference. The clock branch circuit is composed of two resistors to obtain the intermediate voltage of the clock signals on both clock interconnections, and PMOS and NMOS transistors each having a gate provided with the intermediate voltage. These transistors compose a CMOS inverter from which the generated clock signal is taken out.
However, the clock distribution circuit which is disclosed in Japanese Laid-open Patent Application No. 4-229634 still has a problem of requiring a large interconnection area to accommodate two loops which are formed by the two clock interconnections. In addition, the circuit is vulnerable to noise because clock signals on the two clock interconnections are applied to the common gates of the PMOS and NMOS transistors via each resistor.